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100G QSFP28 Direct Attach Cable - MCU(DAC)

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產品型號FGT-100GSFP28-DAC1M

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更新時間:2022-04-04 21:34:56瀏覽次數:486次

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產品簡介

GeneralDescriptionQSFP28passivecoppercableassemblyfeatureeightdifferentialcopperpairs

詳細介紹

General Description

QSFP28 passive copper cable assembly feature eight differential copper pairs,providing four data transmission channels at speeds up to 28Gbps per channel,and meets 100G Ethernet,25G Ethernet and InfiniBand Enhanced Data Rate(EDR) requirements.Available in a broad rang of wire gages-from 26AWG through 30AWG-this 100G copper cable assembly features low insertion loss and low cross talk.

Designed for applications in the data center,networking and telecommunications markets that require a high speed,reliable cable assembly,this next generation product shares the same mating interface with QSFP+ form factor ,making it backward compatible with existing QSFP ports.QSFP28 can be used with current 10G and 14G applications with substantial signal integrity margin


Features and Benefits

l Compatible with IEEE 802.3bj and InfiniBand EDR

l In accordance with the paging function in the protocol SFF-8636, paging can be selected 00H or 02H in 127 bytes

l Supports aggregate data rates of 100Gbps

l Optimized construction to minimize insertion loss and cross talk

l Backward compatible with existing QSFP+ connectors and cages

l Pull-to-release slide latch design

l 26AWG through 30AWG cable

l Straight and break out assembly configurations available

l Customized cable braid termination limits EMI radiation

l Customizable EEPROM mapping for cable signature

l RoHS compliant

Product Applications

l Switches,servers and routers

l Data Center networks

l Storage area networks

l High performance computing

l Telecommunication and wireless infrastructure

l Medical diagnostics and networking

l Test and measurement equipment

Industry Standards

l 100G Ethernet(IEEE 802.3bj)

l InfiniBand EDR

l SFF-8665 QSFP+ 28G 4X Pluggable Transceiver Solution(QSFP28)

Technical Documents

l 108-32081 QSFP28 Copper Module Direct Attach Cable Assembly

High Speed Characteristics

Parameter

Symbol

Min

Typical

Max

Unit

Note

Differential Impedance

TDR

90

100

110

?


Insertion loss

SDD21

-22.48



dB

At 12.8906 GHz

Differential Return Loss

SDD11

SDD22



See 1

dB

At 0.05 to 4.1 GHz



See 2

dB

At 4.1 to 19 GHz

Common-mode to common-mode output return loss

SCC11

SCC22



-2

dB

At 0.2 to 19 GHz

Differential to common-mode

return loss

SCD11

SCD22



See 3

dB

At 0.01 to 12.89 GHz



See 4

At 12.89 to 19 GHz

Differential to common Mode

Conversion Loss

SCD21-IL



-10

dB

At 0.01 to 12.89 GHz



See 5

At 12.89 to 15.7 GHz



-6.3

At 15.7 to 19 GHz

Notes:

1. Reflection Coefficient given by equation SDD11(dB) < -16.5 + 2 × SQRT(f ), with f in GHz

2. Reflection Coefficient given by equation SDD11(dB) < -10.66 + 14 × log10(f/5.5), with f in GHz

3. Reflection Coefficient given by equation SCD11(dB) < -22 + (20/25.78)*f, with f in GHz

4. Reflection Coefficient given by equation SCD11(dB) < -15 + (6/25.78)*f, with f in GHz

5. Reflection Coefficient given by equation SCD21(dB) < -27 + (29/22)*f, with f in GHz

Pin Descriptions

QSFP28 Pin Function Definition

Pin

Logic

Symbol

Description

1


GND

Ground

2

CML-I

Tx2n

Transmitter Inverted Data Input

3

CML-I

Tx2p

Transmitter Non-Inverted Data Input

4


GND

Ground

5

CML-I

Tx4n

Transmitter Inverted Data Input

6

CML-I

Tx4p

Transmitter Non-Inverted Data Input

7


GND

Ground

8

LVTTL-I

ModSelL

Module Select

9

LVTTL-I

ResetL

Module Reset

10


Vcc Rx

+3.3V Power Supply Receiver

11

LVCMOS-

SCL

2-wire serial interface clock

I/O

12

LVCMOS-

SDA

2-wire serial interface data

I/O

13


GND

Ground

14

CML-O

Rx3p

Receiver Non-Inverted Data Output

15

CML-O

Rx3n

Receiver Inverted Data Output

16


GND

Ground

17

CML-O

Rx1p

Receiver Non-Inverted Data Output

18

CML-O

Rx1n

Receiver Inverted Data Output




19


GND

Ground

20


GND

Ground

21

CML-O

Rx2n

Receiver Inverted Data Output

22

CML-O

Rx2p

Receiver Non-Inverted Data Output

23


GND

Ground

24

CML-O

Rx4n

Receiver Inverted Data Output

25

CML-O

Rx4p

Receiver Non-Inverted Data Output

26


GND

Ground

27

LVTTL-O

ModPrsL

Module Present

28

LVTTL-O

IntL

Interrupt

29


Vcc Tx

+3.3V Power supply transmitter

30


Vcc1

+3.3V Power supply

31

LVTTL-I

LPMode

Low Power Mode

32


GND

Ground

33

CML-I

Tx3p

Transmitter Non-Inverted Data Input

34

CML-I

Tx3n

Transmitter Inverted Data Input

35


GND

Ground

36

CML-I

Tx1p

Transmitter Non-Inverted Data Input

37

CML-I

Tx1n

Transmitter Inverted Data Input

38


GND

Ground

Functions realized by MCU

The paging storage function is realized through the MCU. According to the specification of the SFF-8636 protocol, the paging selection function is 127 bytes, and the selectable pages are 00H and 02H. As shown below:

Length (m)

Cable AWG

1

30

2

30

3

26/30

4

26

5

26



Regulatory Compliance

Feature

Test Method

Performance

Electrostatic Discharge (ESD) to the Electrical Pins

MIL-STD-883C Method 3015.7

Class 1(>2000 Volts)

Electromagnetic Interference(EMI)

FCC Class B

Compliant with Standards

CENELEC EN55022 Class B

CISPR22 ITE Class B

RF Immunity(RFI)

IEC61000-4-3

Typically Show no Measurable Effect from a 10V/m Field Swept from 80 to 1000MHz

RoHS Compliance

RoHS Directive 2011/6/5/EU and it's Amendment Directives 6/6

RoHS 6/6 compliant


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